Implementation Workspace — automated design review

Video transcript

00:00 — The Implementation Workspace

The Implementation Workspace. Reviewing schematics, simulations and layouts.

00:09 — Welcome to your Implementation Workspace

This is where you bring schematics, SPICE simulations and PCB layouts for an end-to-end review. It is the one place on Creopus where you ask the AI to judge an implementation rather than generate one.

00:27 — Link to a hierarchy node first

Before the AI review can run, the workspace has to be attached to a node in your System Hierarchy. The AI grounds every judgment against that node's requirements, DFMEA, block diagram and BOM — so the same schematic is reviewed differently depending on whether you link it to an automotive subsystem or a medical one.

00:54 — At-a-glance status

Four numbers give you the state of the review — sub-artifacts uploaded, total findings raised, how many are still open, and how many of those are critical. Baseline the workspace whenever you want a frozen reference to come back to.

01:13 — Upload a schematic

Three ways in — paste a netlist, load a file, or attach a PDF or photo of a hand-drawn schematic for the AI to read visually. Around fifty automated and pattern checks run instantly on any netlist it can parse, covering floating nets, missing decoupling, multiple drivers on one net, and more.

01:37 — Upload a SPICE deck

Paste an LTspice, ngspice or QSpice deck. Hygiene rules check transient step size, AC sweep coverage against your RC corners, ground reference and model definitions. Attach waveform screenshots if you want the AI to judge whether the deck actually exercises what you intended.

02:02 — Upload a PCB

Four formats — KiCad, a Gerber zip straight from your fab package, ODB plus plus, or IPC 2581. Automated rules check board outline, trace width, annular ring, drill sizes and copper-to-edge clearance. Pattern checks add decoupling proximity, via-in-pad, and real clearance computed from exact geometry.

02:29 — Your uploaded artifacts live here

Every upload becomes a sub-artifact card, showing its parsed component and net counts and a chip for each attached file. Delete one to re-upload, and its automated findings go with it — the AI findings persist until you re-run the review.

02:51 — AI schematic review

After the instant checks, this runs the grounded AI review. It reads your requirements, DFMEA, block diagram, BOM and any attachments, then judges whether the schematic actually realises the stated intent. It stays disabled until you have linked a node and uploaded a schematic.

03:15 — AI layout review

Same grounding — different surface. The layout reviewer judges the parsed board (or Gerber / ODB++ / IPC-2581) against the same requirements, DFMEA, block diagram and BOM. It comments on routing decisions, EMC tradeoffs, DFM, and whether the layout is consistent with the schematic and sim already in the workspace.

03:47 — AI cross-check

Once you have uploaded at least two of schematic, simulation and layout, this runs a consistency review across them. It surfaces what no single-artifact reviewer can see — a schematic net the simulation never references, or a layout footprint that disagrees with the schematic.

04:09 — Findings — discipline, disposition, discussion

Every review tier funnels into one Findings list, grouped by severity. Each finding carries a discipline badge — Electrical, Layout or Mechanical — and the chips at the top filter by who is responsible. Disposition a finding as accept, reject, defer or note and it collapses, so the open ones stay in focus. You can edit an AI finding without losing its provenance, add one the AI missed, and use the discussion thread inside a finding for the back-and-forth while a fix is in flight.

04:47 — AI follow-on — focused directives

Used the canned review buttons above and want to re-run with a more specific lens? Pick one of the canned directives (e.g., "flag any rail without dedicated decoupling") or write your own — the AI re-runs against the same hierarchy context but biased toward your directive. Existing findings are preserved; new ones inherit the directive's framing in their citations.

05:16 — Multiple workspaces

Each implementation review lives in its own workspace. Click + New workspace to start a fresh one — your past workspaces stay one hamburger-click away (top-left). You can have parallel workspaces for different blocks of the same product, or revisit older reviews to mine their findings.

05:39 — docs.creopus.ai

Full documentation, including every tool, is at docs.creopus.ai

What it does

Every other tool in Creopus helps you produce a document. The Implementation Workspace does the opposite: you upload the design you have actually built — schematic netlist, PCB layout, SPICE deck — and it reviews it, producing structured findings against your own requirements and DFMEA.

It is a second pair of eyes that has read your requirements, at three in the morning, without getting bored on page forty.

Why it matters

Design review is where hardware teams lose the most time and catch the fewest problems. A senior engineer reads a schematic for an hour, spots six things, and misses the missing decoupling cap on page four because nobody can hold a whole board in their head.

The reviews that scale are the boring, deterministic ones — is every net driven, is the annular ring above the fab's floor, does the .tran window actually cover the RC time constant. Those should never have needed a human. What a human is genuinely good at is judgement, and judgement is what is left once the mechanical checks are done.

This is also the part of Creopus that no requirements tool does. Requirements platforms manage text about your design; layout tools work on the design but have never read your requirements. The Implementation Workspace sits in between.

What it reads

24 parsers, so it takes the files you already have rather than asking you to export something special:

• Schematic — KiCad (XML and legacy, multi-sheet), Altium .SchDoc, Protel, Qucs, LTspice, QSpice
• Layout — KiCad .kicad_pcb, Gerber (RS-274X, zipped), Excellon drill, ODB++, IPC-2581, Altium .PcbDoc
• Simulation — SPICE decks, Cadence Spectre

Format is auto-detected. Large files go to object storage rather than into the document.

How the review works

Three layers, each doing what it is actually good at:

Layer 1 — deterministic rules. 32 schematic rules, 14 layout rules, 13 simulation rules. Floating nets, multi-driver conflicts, outputs tied to power rails, trace width below the floor, annular ring, copper-to-edge clearance, unrouted nets, model references that do not exist, transient analyses with no transient source. These either fire or they do not — reproducible, explainable, no model involved.

Layer 2 — curated patterns. 29 schematic and 19 layout patterns encoding the things experienced engineers check by habit: LDO bypass caps, I²C pull-ups, crystal load caps, MOSFET gate resistors, decap proximity, via-in-pad, thermal-pad vias, mounting-hole isolation, real DRC clearance backed by spatial indexing, and copper pour imbalance computed from actual flood-fill area rather than an estimate.

Layer 3 — grounded LLM review. Only here does a model get involved, and only with your requirements, DFMEA, block diagram and BOM in front of it. It is asked to judge whether the implementation actually realises what those documents promised — the question a deterministic rule cannot ask.

There is also a cross-artifact pass that checks the schematic, simulation and layout against each other: do the references match, does the sim exercise the circuit that was drawn, does the layout implement the schematic.

What you get back

Findings, each with a severity (critical / major / minor / editorial), a category, the layer that produced it, a location, a recommendation, and a discipline tag (electrical / layout / mechanical) so the right person sees the right subset.

A real run against an 11-component, 14-net flight-computer schematic: 19 findings in a few seconds, 12 from deterministic rules and 7 from curated patterns. F-8 caught a resistor with one pad floating; F-14 caught an I²C net with no pull-up — an open-drain bus that would simply never communicate. Filter by discipline so layout engineers are not reading electrical findings, and dispose of each one like a review comment.

Findings are dispositioned like review comments — open → accepted / rejected / deferred / noted, with reason and audit fields — and each carries its own comment thread, so the EE-to-layout conversation lives with the finding instead of in a chat log. Findings can link to the specific requirement or DFMEA failure mode they relate to.

You can add findings by hand too. A manual finding is marked as human-authored, and that provenance survives editing, so "did a person or the machine flag this?" always has an answer.

Getting started

Create an Implementation Workspace on the hierarchy node whose design you are reviewing — the node context is what makes Layer 3 useful. Upload a schematic first; Layers 1 and 2 run immediately, and the LLM review runs in the background and appears when it completes. Add the layout and simulation as they exist, and the cross-artifact checks become available once you have more than one.